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Job Description
Analog Layout Engineer
A fantastic opportunity for an experienced Layout Engineer to join a rapidly growing Technology Company who specialise in the design of cutting-edge oscillator ASICs that sit at the heart of their world-leading precision timing products.
You will work alongside a team of bright minds, onsite in Cambridge, UK.
Responsibilities will include:
- Layout of blocks within the ASIC while considering the block interfaces on the top level through good communication with layout lead and design engineer.
- Running block and top-level layout checks and solve flagged errors.
- Contribute to the layout process continuous improvement by identifying opportunities and participate in and/or proactively lead initiatives.
- Floor planning of the ASIC.
Ideally you will have:
- A Bachelor, Master or PhD degree in Electronics Engineering or related subject.
- Over 5 years of hands-on experience with analogue circuit layout in CMOS and Bi-CMOS technologies.
- Be a team player with good interpersonal skills, and excellent communication skills, including verbal, written and communication, and presentation skills in English.
- Very good knowledge of Cadence tool workflow for schematic capture and layout XL.
- Very good knowledge in running tool for checking DRC, LVS, ERC and antenna rules and ability to effectively debug any errors
- Very good knowledge of good layout matching techniques such as common centroid or dummy usage
- Very good understanding of electromigration and how to layout a block with high reliability
- Appreciation and knowledge of parasitic associated with a layout.
- Knowledge of Cadence SKILL language and PCELL development.
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