Job Description
Job Description
My client design cutting-edge ASICs that sit at the heart of our world-leading precision timing products. We are looking for a Senior ASIC Layout Engineer with the skills and enthusiasm to significantly enhance the competitive position by delivering robust, high-performance custom analogue and mixed-signal integrated circuits.
About the client and position:
As an ASIC Layout Engineer, you would play an integral role of bringing the designs into silicon. You will be working closely with the design team and the Layout Lead to decide the layout requirements and achieve the task efficiently and with minimum risk. The ideal layout engineer would have had previous professional experience in a high-volume production environment with a sound understanding of ASIC design and development flow.
Responsibilities:
* Layout of blocks within the ASIC while considering the block interfaces on the top level through good
communication with layout lead and design engineer.
* Running block and top-level layout checks and solve flagged errors.
* Contribute to the layout process continuous improvement by identifying opportunities and participate
in and/or proactively lead initiatives.
* Floor planning of the ASIC.
Requirements:
* A Bachelor, Master or PhD degree in Electronics Engineering or related subject.
* Over 5 years of hands-on experience with analogue circuit layout in CMOS and Bi-CMOS
technologies.
* Be a team player with good interpersonal skills, and excellent communication skills, including verbal,
written and communication, and presentation skills in English.
* Very good knowledge of Cadence tool workflow for schematic capture and layout XL.
* Very good knowledge in running tool for checking DRC, LVS, ERC and antenna rules and ability to
effectively debug any errors
* Very good knowledge of good layout matching techniques such as common centroid or dummy
usage
* Very good understanding of electromigration and how to layout a block with high reliability
* Appreciation and knowledge of parasitic associated with a layout.
* Knowledge of Cadence SKILL language and PCELL development.